[stella] 6532 spec

Subject: [stella] 6532 spec
From: Dan Boris <dan.boris@xxxxxxxx>
Date: Mon, 11 Aug 1997 12:22:05 -0400
Last week someone asked for some more info on the 6532 RIOT chip.

This information comes from a book by Rockwell about thier AIM
Microprocessor trainer.

RAM Addressing
---------------------------------
RS=0
RW=1 to read, RW = 0 to write
A0-A6 select RAM address


I/O Addressing
---------------------------------
RS=1, A2=0
RW=1 to read, RW=0 to write

A0  A1
0   0     PA data
1   0     PA data direction (1=Output/0=Input)
0   1     PB data
1   1     PB data direction (1=Output/0=Input)


Write Edge-Detection Control
---------------------------------
RS=1, A2=1, RW=0, A4=0

A1=1: Enable interrupt from PA7
A1=0: Disable interrupt from PA7
A0=1: Positive edge detect
A0=0: Negative edge detect

Read and Clear Interrupt Flag
---------------------------------
RS=1, RW=1, A2=1, A0=1

Bit 7 = Timer IRQ flag
Bit 6 = PA7 IRQ flag

Write Count to Interval Timer
---------------------------------
RS=1,A4=1,A2=1, RW=0


A0  A1
0   0     Divide by 1     
1   0     Divide by 8
0   1     Divide by 64
1   1     Divide by 1024

A3=1 Enable timer interrupt
A3=0 Disable timer interrupt


This table did not saying anything about reading from the timer but the 
text of the book does mention it. From experience with the Atari 2600 I 
think the timer can be read at:

RS=1,A4=1,A2=1,RW=1  (Timer start registers) 
and
RS=1,A2=1,A0=1 

The only thing I saw in here that could be potentiolly useful is the
Interrupt flag register. When the timer reaches zero bit 7 of this
register is set to 1 and stays that way until it is read. This seems to
be an easy way to tell when the timer has expired, surprised no one (to
my knowledge) has used it.

						Dan Boris

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