Well this doesn't seem to have gone through, even though I sent it on 1/19/00
so here it is again. It probably got caught in the spam trap since I included
an URL in it so I will disguise the URL. Also, I made one minor change.
---
Well, I have completed the schematic for the ROMBlaster. The circuit has not
been tested however it should work theoretically. :-) If I get some time
later in the week I can test it however.
Refer to the schematic during the following explaination:
w#w#w#.##p#a#r#o#d#i#u#s#.#c#o#m#/~k#h#o#rton/ro#m#b#last.gi#f#
It uses just three chips- a 7408, 7402, and a 74245 (a '244 would work as well
though the '245 has a nicer "Straight-thru" pinout).
Also, /CE and /OE on the cart's ROM are tied to ground. All enabling is
done through the '245.
Method of operation: Operation is simple. When the power is first turned on,
the .1uf cap is essentially a short since it is fully discharged. This is
used as a reset for the set/reset flipflop which is composed of LS02a and
LS02b. This enables LS08a and disables LS08b. LS08c detects a processor
read and this passes through LS02d to the LS245 latch, enabling it. (LS02d
also inverts the signal to give us a proper active low enable)
A processor read is when both phi2 and R/W are high. Detecting this is
important, because if we did not, the writes to the latch would not proceed
due to our ROM overpowering the bus :-). This makes sure writes will succeed.
A15 coming off the cart line is not really A15 (pin 1 on the connector). It
is the output of an AND gate. Its product is A15 AND /CE on the internal
BIOS ROM. So when the system first powers up, it is LOW. This signal passes
through an inverter made up of LS02c, into the other leg of our S/R flipflop.
When the internal BIOS is on, the A15 line is low, which gets inverted
so the input to our S/R is high. (the S/R has active low inputs)
When the internal BIOS is off and we are executing code anywhere in 8000-ffff,
this line will be high. Inverted, this means the input to our S/R will be low,
forcing it to switch states. This disables the phi2/R/W thingy and enables
A15 decoding (LS08b). Now when A15 is high, the enable on the '245 will be
low, enabling our ROM. all other times it will be low (disabling the '245).
This circuit was designed for a 32K ROM, though it should work on 8, 16, and
32K ROMs. (I also assumed 8000-ffff was cart space. Correct me if I'm wrong
on this (so I can fix the circuit and code example)
The startup code for this thing would look something like this:
.org 8000
start: lda #0000 1110b ;disable BIOS, enable sel 3, A12 on cart
sta 03fh ;write to port
lda #0000 1101b ;same as above plus "lockout" bit
sta 03fh ;all stuff is enabled, latch disabled
ldx #0ffh
txs ;normal stack stuff
cld ;no decimal
ldx #0
ldy #0
loop1: dex
bne loop1
dey
bne loop2 ;delay to make sure reset is over
... rest of your code follows ...
NMI: rti ;our NMI routine
IRQ: rti ;our IRQ routine
.org 0fffah
.dw NMI ;NMI vector
.dw start ;start vector of our code
.dw IRQ ;IRQ vector
Some notes: A12, A14, and A15 will be *LOW* when the code first runs due to
those AND gates on these lines. A13 passes through and does not
go through an AND gate. This means you have to write you code
to run somewhere in 10x0 xxxx xxxx xxxxb. I chose 8000 since it's
the beginning of ROM, and satisfies the above critera. Note that
A15 is low, but since we are using phi2 AND R/W this does not
count :-)
The delay loop at the beginning is to make sure the capacitor on
the reset circuit is fully charged to prevent it from switching
the state of our flip-flop after the cart has come up.
Note that the data bus is only overridden during the vector fetch
and for the first two instructions. After that, the internal ROM
is disabled and all is right with the world. This will take
close to 10 *microseconds*. That's 10 millionths of a second.
Once started, the IRQ and NMI vectors can point wherever you want
them to. They will be read out of the ROM like normal without
incident.
Note that I did not include an SEI instruction. One is not
required. When a 6502 is reset, it is automatically SEI'd for
you. :-)
And the vectors will need to be located two places in the ROM-
one with A12 and A14 both low. (AFFC, AFFD for the reset vector.)
That is all, enjoy!
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