[stella] TIA Schematic
Subject: [stella] TIA Schematic|
From: Kevin Horton <khorton@xxxxxxxxxxx>
Date: Tue, 18 Sep 2001 00:37:37 -0500
Well, I finally got them. 5 sheets of "D" size drawing goodness. I have
done a preliminary appraisal of the circuit and it's much simpler than I
though it was going to be. I found some interesting (to me, anyways :-)
things about the TIA which others may want to know.
Alot (all? some?) of this info was already known but it's neat to actually
see how it was implemented back in the day.
1) When reading, only D6 and D7 are used. period. The chip only has
readback buffers for D6 and D7, and D0-D5 just hang in the breeze. So, if
you are going to do an absolute comparison (instead of using the
preferrable BIT or LDA/BPL/BMI tricks, which you SHOULD use) you must AND
off the lower 6 bits; i.e.
AND #0C0h ;strip all but two upper bits
Both bits are output during a read to ANY TIA address... if nothing happens
to be decoded, then 0's are returned. Ditto for any register that only has
1 bit worth of info.
2) The object position counters are LFSR's, which output a non-linear
count. The one for the ball is 6 bits with feedback taken from bits 4 and 5.
3) All graphics are serialized before reaching the video logic. Said logic
uses a priority encoder to decide which colour register is sent on to the
colour encoder to produce the proper phase shift. Luma info is passed
straight out 3 pins on the chip, only being latched with the pixel clock on
4) There are craploads of wire-ANDed and wire-OR'd "gates" on this chip :-).
The sheer amount of "Mickey Mouse Logic" (M^2L) is staggering. This is
when you make logic gates out of discrete transistors, diodes, and resistors.
5) The player graphics scan counter is a simple 3 bit binary counter, and
they did a really cute trick to reverse the graphics in "reflect"
mode. The Q outputs are used to get the desired bit in "normal" mode, but
the /Q outputs are used to get the desired bit in "reflect"
mode. (Inverting all outputs of a binary counter will turn an up-counter
into a down-counter, and vice-versa)
6) There are 6 serial video sources on the chip- playfield, player 0/1,
missile 0/1, and the ball.
7) Collisions are detected by ANDing the afore-mentioned serial graphics
together, and if the result of the AND is true, a flip-flop made out of two
cross-connected NOR gates is set. All collision register clear lines are
connected together and all the registers are cleared at the same time.
8) The horizontal scan counter is an LFSR, like most of the other counters
on this chip. Certain counts are decoded to produce the colourburst,
horizontal synch, and the other scanline timing.
9) Playfield graphics are neat. They simply used a 20 bit left/right shift
register to produce the PF graphics. This allows both "normal" and
"reflected" versions to be produced. The clock for this is taken directly
from the clock to the horizontal scan counter.
10) Most of the hard logic decisions, like collision detection and the
horizontal synch/colourburst/timing are done using programmed AND arrays.
There are more things, but those are the ones that jumped right out at me
on a cursory inspection.
Interestingly, I saw the player graphics registers, specifically the "new"
and "old" copies (their term) which makes 6 sprites on a scanline and other
nifty tricks, possible. I *think* they use a 2 level deep * 8 bit shift
register for this (will need to do more reading later).
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