Re: [stella] Midified VCS...

Subject: Re: [stella] Midified VCS...
From: Chris Wilkson <ecwilkso@xxxxxxx>
Date: Tue, 20 Nov 2001 20:47:06 -0500 (EST)
On Tue, 20 Nov 2001, Glenn Saunders wrote:

> >it does not seem to be that complex.
>
> The TIA chip has approximately 10,000 gates.
>
> That's pretty time-consuming to recreate by one person, I think.

Heh...yer damned right, Pilgrim!!

I'm spending about 10-15 hours a week on this project.  (Whoa!  Did
anyone hear that?  Chris is spending more than 5 minutes a week on
an Atari project!!!)  The good news here is that because I know what
one section is doing, it's a lot easier to do the next section.

The "5 pages of schematics" thing is kinda misleading.  Because those
5 pages consist of cell schematics that are then copied X,Y, or Z times
as tiny little "black boxes".  And they consist, in part, of circuitry that
you can't do in an FPGA without wasting gates.  And they consist, in part,
of circuitry that you can't do in an FPGA at all.  And I've found one
place where it looks like the ESD device is actually part of the
functionality.  YUCK!

I'm starting to think laying out an ASIC would be easier than doing it
in VHDL.  I dunno.  But the good news is that I'm on target to start
drawing pictures with this thing in late January or February.  Woohoo!

Go Sooners!  (college football, for those of you outside the US)

-Chris

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