Subject: Re: [stella] Reverse engineering the TIA (Was: Midified VCS...) From: Kevin Horton <khorton@xxxxxxxxxxx> Date: Fri, 07 Dec 2001 00:23:16 -0500 |
Hello Mark!
I intend to redesign it using 74xx IC's (don't laugh...) . Preferably F-Types.
Well, i looked at the counters, and they indeed consist of 6 self-feedbacked shift registers, driven by a two phase clock , using some kind of wired-and logic to decode various states. Fortunately, J. Miner wrote at the H-Sync
The bus logic and sync decoding are not really a problem to do in TTL. The Playfield registers are tricky. Could be replaced by latches and a flip-flop chain, which is logically anded with the outputs of the latches.
Sheet 2 consist mainly of the Bus drivers, the collision detection, and the address decoding. The adress decoding consist again of primitive wired and logic. TO do it in an FPGA, you'll have to convert it to real AND gates (which will significantly increase the gate count). I intend to use 4 plain 74154 4 to 16 address decoders... (yuck).
In the last sheet, there are 4 7-bit registers for the color data. Above is the priority logic, which selects the color register. My prototype will have the color phase delay logic replaced by two PROMS, where the colors are hardcoded (as i said).
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