On Fri, 28 Feb 2003, Eric Ball wrote:
> There are a couple of ways that FE bankswitching could work. The simplest
> would be for AddBus=01FF followed by 01FE selects one bank, while 01FE
> followed by 01FF selects the other. But if the existing code allows the
> primary bank to JSR to subroutines in the same bank as well as switching
> banks, then maybe it is watching the data bus as well. The read immediately
> following 01FE gives the bank on the JSR, and the same is also true for the
> RTS.
You must watch the data bus; there are JSR/RTS within the same bank.
> The timing of the bankswitch should also be considered. On the JSR, the
> bankswitch occurs between cycle #5 & 6. On the RTS it can happen either
> between cycles #4 & 5 or #5 & 6. This suggests that the bankswitch hardware
> has at least the "intelligence" to count cycles, since the JSR bankswitch
> happens a cycle after the 01FF/01FE trigger. (It wouldn't be too hard to
> create a PLL based on the address bus LSB.) This would also make it
> possible to read the bank from the data bus.
Carts don't/can't/shouldn't count cycles. They should watch for address
line changes only. All the carts I've dumped so far do this.
Guru meditiation: stx WSYNC
> If this were true, it should be possible to implement 32K ROMs using "FE+"
> bankswitching. Don't know how difficult the logic would be though. It
> would require more than a standard 22V10 PAL though... unless it monitors
> less than the full address & data bus, hmm... maybe only D7 D6 D5 (bank)
> A12 (ROM/RAM) A8 (zero page & RIOT / stack) and A0 ( PLL ). Load the bank
> register from [D7 D6 D5] on the cycle after two consecutive A12 = 0 & A8 = 1
> accesses. Sounds possible at least.
16K ROM only for FE+. The address line A22 must be high, which nukes half
your address space. i.e. the cart cannot see the difference between accesses
to $0000 and $E000.
--
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