[stella] I think I got F8 bankswitching to work.

[Aaron Bergstrom <aaron.bergstrom@xxxxxxxxxxxxxx>]

Alright, I think I understand this now. Attached to this message is my 
attempt at F8 bankswitching. Surpisingly, this bin works on both the 
Stella and Z26 emulators. Can someone check this for me to see that I 
wrote it properly? All this binary does is change the background color 
from yellow to blue every four seconds or so.

Thanks for the info Thomas,

Aaron

Thomas Jentzsch wrote:

> Aaron Bergstrom wrote:
>  
>
> > But I'm not clear on how the ASM file is to be structured so that each
> > bank has an address of $1000 to $1FF3.
> >    
>
> That's no problem, because due to addressing space limitations of the
> 6507, e.g. $1000 = $3000 = $5000...
>
> You must logical ORG your banks at an odd 4K segment (else you might
> access the TIA, RAM etc.)
>
> E.g. ORG $1000 for the first bank and $3000 for the second bank works
> good. But some standard is to use the last possible addresses, so you
> should use $d000 and $f000 for 8K games.
>
> Now it get's a bit more complicated:
> The examples about would create 12K instead of 8K files, because you
> skip the $2000 or $e000 bank and the assembler will fill that with $FF.
>
> But there is RORG. This one is getting important for bankswitched games,
> because it's only a logical origin and not a also physical one.
>
> So your banks could start e.g. like this:
>  ORG $1000
>  RORG $d000
>  ...
>  ORG $2000
>  RORG $f000
>
> Note that you *always* must use ORG and RORG then.
>
> Now all you code is assembled for the logical origin, but stored at the
> physical one and you get a 8K file.
>
> Have fun!
> Thomas                            
> _______________________________________________________
> Thomas Jentzsch         | *** Every bit is sacred ! ***
> tjentzsch at web dot de |
>
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>  

	processor 6502
	include vcs.h

SC = $80

	org $1000
	rorg $d000

MainLoop2
VSyncSetup2
	LDA #2
	STA VSYNC
	STA WSYNC
	STA WSYNC
	STA WSYNC
	LDA #43
	STA TIM64T
	LDA #0
	STA VSYNC
VBlankWait2
	LDA INTIM
	BNE VBlankWait2
	LDA #1
	LDY #191
	STA WSYNC
	STA VBLANK
BurnToEnd2
	STA WSYNC
	DEY
	BNE BurnToEnd2

	LDA #2
	STA WSYNC
	STA VBLANK

	LDY #30
OverScan2
	STA WSYNC
	DEY
	BNE OverScan2

	LDA #240
	DEC SC
	BIT SC
	BEQ Next2
	JMP MainLoop2
Next2
	JMP ChangeColor2

	org $1100
	rorg $d100
ChangeColor2
	STA SC
	LDA $1ff9
	nop
	nop
	nop
	nop
	nop
	nop
	LDX #$72
	STX COLUBK
	JMP MainLoop2
	
	org $1fff
	rorg $dfff

;---------------------
;Bank 2
;---------------------

	org $2000
	rorg $f000

Start
	SEI
	CLD
	LDX  #$FF
	TXS
	LDA  #0

ClearMem
	STA 0,X 
	DEX    
	BNE ClearMem
	LDA #240
	STA SC
	LDA #$FE
	STA COLUBK

MainLoop
VSyncSetup
	LDA #2
	STA VSYNC
	STA WSYNC
	STA WSYNC
	STA WSYNC
	LDA #43
	STA TIM64T
	LDA #0
	STA VSYNC
VBlankWait
	LDA INTIM
	BNE VBlankWait
	LDA #1
	LDY #191
	STA WSYNC
	STA VBLANK
BurnToEnd
	STA WSYNC
	DEY
	BNE BurnToEnd 

	LDA #2
	STA WSYNC
	STA VBLANK

	LDY #30
OverScan
	STA WSYNC
	DEY
	BNE OverScan

	LDA #240
	DEC SC
	BIT SC
	BEQ Next
	JMP MainLoop
Next
	JMP ChangeColor

	org $2100
	rorg $f100
ChangeColor
	STA SC
	LDA $1ff8
	nop
	nop
	nop
	nop
	nop
	nop
	LDX #$FE
	STX COLUBK
	JMP MainLoop
	
	org $2ffc
	rorg $fffc
	.word Start
	.word Start

Attachment: banktest16.bin
Description: Binary data