## Re: [stella] TIA Audio Polynomials

 Subject: Re: [stella] TIA Audio Polynomials From: David Date: Wed, 19 Nov 2003 02:10:43 -0800

Using these Linear Feedback Shift Registers for many of the counters in the TIA (Horizontal Sync, Player/Missile position) was pretty neat. It was very crafty of the Atari engineers to get 'n' states with just a shift register and a couple of extra gates. For the player position counter there seem to be three extra gates (not including an inverted output that's 'for free').

Looking at the schematic you can see these LFSRs for player position. I have included some code to emulate the logic below.

For the Audio section, once again looking at the schematic it appears that with some work, it should be possible to directly infer the exact logic for the 9 bit polynomial setting? I can see a section with 5 bits and what looks like two taps on bits 2 and 4 (counting from zero). Below to the right appears to be another section with four flip flops which appear to be cascaded. My hunch is that the 5 bit and 4 bit sections are perhaps combined for the 9 bit operation. The four AUDC0 control bits are clearly labeled and feed into the logic which controls the registers. I'd need to puzzle it out some more because some of the wired logic and transistor logic I don't understand. Perhaps someone else who is more qualified could take a look?

- David Galloway

Just because it's related, here is some Python code that implements the Player Position Counter LFSR. Below I include the output, which should be familiar.

def EOR(a,b):
return a^b
def AND(a,b):
return a & b

#quick and dirty binary output
def bpr(value):
string = ""
for bit in range(0,6):
tbit = pow(2, bit)
if (AND(tbit, value)):
nbit = "1"
else:
nbit = "0"
string = nbit + string
print string,
reg = 0

for count in range(0,64):
bpr (reg)
print
bit0 = AND(reg,0x01)
bit1 = int(AND(reg,0x02) >> 1)
nbit6 = (not(EOR(bit0,bit1))) * pow(2,5)
reg = reg >> 1
reg = reg + nbit6
000000
100000
110000
111000
111100
111110
011111
101111
110111
111011
111101
011110
001111
100111
110011
111001
011100
101110
010111
101011
110101
011010
001101
000110
000011
100001
010000
101000
110100
111010
011101
001110
000111
100011
110001
011000
101100
110110
011011
101101
010110
001011
100101
010010
001001
000100
100010
010001
001000
100100
110010
011001
001100
100110
010011
101001
010100
101010
010101
001010
000101
000010
000001

Thomas Jentzsch wrote:

On Tuesday, November 18, 2003 at 21:17, Adam Wozniak wrote:

The next step up would require four taps (maximal sequences always have
an even number of taps). Easier to do an XOR gate with a smaller number
of taps?

```I have almost no idea about how to implement an LFSR. But I thought
there might be a reason like the one you just mentioned. Thanks for
confirming my idea. :-)```

So they did some hardware optimization there. Cool!

Have fun!
Thomas _______________________________________________________
Thomas Jentzsch | *** Every bit is sacred ! ***
tjentzsch at web dot de |

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