Subject: RE: [stella] 6502 question (was INV+ ... ) From: Chris Wilkson <ecwilkso@xxxxxxx> Date: Thu, 8 Apr 2004 02:48:36 -0400 (EDT) |
Lee (and anyone else who's new since the last time I posted this), I have complete memory maps for the VCS at http://web.mit.edu/ecwilkso/www/VCS_hardware -Chris On Wed, 7 Apr 2004, Erik Mooney wrote: > "Lee Fastenau" <stella@xxxxxxxxxxxxxxx> wrote: > > > Why would the RTS read from the collision registers after a JSR that writes > > to RESPx? The Reset registers don't share memory locations with any other > > registers... at least not as far as vcs.h is concerned, so reading from them > > would yield totally unexpected results. Or so I would think. > > > > Is this another undocumented feature (of thousands) of TIA? > > It's documented, just not in vcs.h. The collision (and other > read registers like INPT4) range from $00 to $0E, but are also > mirrored at $10 through $1E and so on up to $70 through $7E. > All the TIA graphics registers (any address between $00 and $7F) > are write-only; any read access to that area reads from a > collision register instead. > > That all happens because to save on silicon gates, the TIA > doesn't do full address analysis for read requests. Because > the graphics registers are write-only, there's no need for it > to distinguish between a read from $00 and $10, so it doesn't. > So if you try to read (any type of read, whether it's LDA or > RTS) from RESP1, which is at address $11, that's the same thing > as reading from $01, which is CXM1P. > ---------------------------------------------------------------------------------------------- > Archives (includes files) at http://www.biglist.com/lists/stella/archives/ > Unsub & more at http://www.biglist.com/lists/stella/ > > ---------------------------------------------------------------------------------------------- Archives (includes files) at http://www.biglist.com/lists/stella/archives/ Unsub & more at http://www.biglist.com/lists/stella/
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