-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
from the TIA manual:
> There are one bit, addressable registers on this chip for vertical sync
> and vertical blank. The timing for these functions is established by
> the microprocessor by writing zero or one into these bits. (VSYNC, VBLANK)
This may sound dumb, but what is the difference between the two?
How does setting one or the other affect the outputs on the TIA pins?
- --
adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam
KG6GZR http://cuddlepuddle.org/~adam/resume.html
"You think grown-ups have it all figured out? That's just a hustle,
kid. Grown-ups are making it up as they go along just like you. You
remember that, and you'll do fine."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.1 (GNU/Linux)
iD8DBQFBYgypyvXf5Z0z5zERAl08AKCfbTKFHTCuY1GXDpWzSFfcz4j5kgCfYoX4
q6hpqrxaaguEcOri7/CRJDc=
=sPwe
-----END PGP SIGNATURE-----
