Hi Fred !
> I thought about that. It does depend on how fast the hardware operates.
> There is only one cycle between $FFF8 and $FFF9 accesses. Standard logic
> chips should be more than fast enough for this, it's just that the
> hardware
> I've seen uses a 0.1 uF capacitor to filter out glitches, and this cap may
> slow down the switching enough to cause this to not work.
I don't agree on that. Look at the timing diagram for an LDA $FFF8:
# address R/W description
--- ------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch low byte of address, increment PC
3 PC R fetch high byte of address, increment PC
4 address R read from effective address
When the LDA $FFF8 is executed, you only have the effective adress
on the bus for one processor cycle. So If the bankswitching hardware does
not switch, if it sees a valid adress for one cycle, it will simply not work
at all :-)
And the 0.1 5F Cap is good for about 3005s delay. I think I calculated that
a while ago.
Don't know the exact value, but it is in that range. It should switch !
Armin
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