No...the DC component is the important part. The coupling is *parasitic*.
As a designer, you wish it wasn't there. But in this application it isn't
super critical. BTW, there is no RC oscillator in the TIA.
Again, I don't have my schematics...they're in Missouri. But I think
that section was done correctly on the publicly available copies so
we can use that. Think of those enhancement pullups as resistors.
Combined with the bottom (driver) transistor, this forms an NMOS
inverter. (And the 2 stacks form a buffer.)
Let's look at a single inverter. Assume the output is low, and that
DEL=5v. That means that VGS of the pullup is 5v. When the input
goes low, the driver turns off. The pullup device is turned on by VGS=5V.
(note: VGS decreases as the output rises, but for this discussion, it's
ok to assume it's constant forever.) So the output begins to rise
because of the "constant" current flowing through the pullup.
Now assume that DEL=2.5v (same situation as before.) Because VGS is only
2.5V now, the pullup is weaker, less current flows, and the output rises
more slowly. It will reach the logic trippoint later. This creates a
delay vs. the previous situation.
That's how the analog delay line in the TIA works.
Now to explain the parasitic ~ 50 MHz noise. When the inverter output
is stable, CGS of the pullup (the parasitic capacitor between the gate
and source) charges to a certain voltage. This voltage can't change
instantaneously. So when the output switches the gate, which is tied
to DEL, must move in the same direction.
This is how charge pumps (a type of voltage converter) work. Here, it's
an undesirable parasite, but elsewhere one can optimize the effect to make
step up, step down, or negating inverters.
This pumping action happens for all 14 delay stages, so there appears to be
a ~ 50 MHz component riding on DEL. But each gate is only a small fraction
of the total parasitic capacitance connected to DEL. The charge in CGS is
shared between CGS and all the other CGS's and parasitics, so the voltage
shift on DEL will be very small. I wouldn't hazard a guess at this point.
-Chris
PS. I keep telling you to get a scope! :P
On Wed, 11 May 2005, Adam Wozniak wrote:
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> On Wed, 11 May 2005, Chris Wilkson wrote:
> > Despite all of this, the delay (pin 10) input is supposed to be a DC
> > voltage. If you actually measure it, it will look like a DC voltage
> > with some high frequency (~50 MHz per above) noise riding on it.
> > Plus any noise that comes from VCC.
>
> I don't think the DC component is the important part. If you look
> at the schematic, the delay line is connected to the gates of several
> transistors in the delay chain.
>
> I think the frequency of the AC component is the important bit.
> Adjusting the pot on the board changes the time constant of a simple RC
> oscillator which generates the delay signal. Each time the delay line
> gets high enough to trigger those transistors, the colorburst frequency
> is shifted down the delay chain.
>
> I really need a scope.
>
> - --
> adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam
> KG6GZR http://cuddlepuddle.org/~adam/resume.html
>
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