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On Fri, 17 Jun 2005, C. Bond wrote:
> According to the docs I have, the time lag (delay) between
> the CPU phase 0 clock, generated by the TIA, and the CPU
> phase 2 clock, generated by the 6507, may be as much as
> 150nsec. This seems excessive. Has anyone ever measured the
> difference? I would appreciate any input from someone with
> other information or the ability to 'scope the hardware.
It is excessive.
I measured it a long while back, and was surprised at how close
phi0 and phi2 really were. Unfortunately my memory isn't perfect,
but I seem to recall a number closer to 15ns than 150ns.
I'll see if I can remember to measure it after work tonight.
- --
adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam
KG6GZR http://cuddlepuddle.org/~adam/resume.html
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