[stella] Clock Skew, redux

Subject: [stella] Clock Skew, redux
From: "C. Bond" <cbond@xxxxxxxxxxxxx>
Date: Thu, 30 Jun 2005 11:19:41 -0400
I was hoping that someone would have the means and
inclination to measure the delay between the 6507 Phase0 and
Phase2 clocks. This delay time seems to have been omitted
from the 650x family of data sheets. Since the 6502 has the
same clock generator as the 6507, maybe someone could
measure it on a Kim-1 or other single board system and post
the results.


C. Bond

P.S. I'm simulating a TIA and need the nominal delay to
check boundary conditions between the CPU Phase2, which
strobes latches, and the divide-by-four clock, which runs
the TIA circuits.

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