Thanks Dan. As I mentioned, the 650x data sheet does not cover this. The TIA docs indicate
something like 150nsec!--but your measurement sound very close to what I would expect.
C. Bond
-----Original Message-----
From: Dan Boris <dboris@xxxxxxxxxxx>
Sent: Jun 30, 2005 3:23 PM
To: stella@xxxxxxxxxxxxxxxxxx
Subject: RE: [personal] [stella] Clock Skew, redux
If my measurements are correct (haven't actually measured anything with
a scope in quite a few years), then it appears the Phase 0 leads Phase 2
by .02us. The Phase 0 signal isn't to clean so it's hard to get a really
accurate point to measure from. Now that I have everything setup let me
know if you need anything else measured.
Dan
> -----Original Message-----
> From: C. Bond [mailto:cbond@xxxxxxxxxxxxx]
> Sent: Thursday, June 30, 2005 11:20 AM
> To: stella@xxxxxxxxxxxxxxxxxx
> Subject: [personal] [stella] Clock Skew, redux
>
>
> I was hoping that someone would have the means and
> inclination to measure the delay between the 6507 Phase0 and
> Phase2 clocks. This delay time seems to have been omitted
> from the 650x family of data sheets. Since the 6502 has the
> same clock generator as the 6507, maybe someone could measure
> it on a Kim-1 or other single board system and post the results.
>
> Thanks,
>
> C. Bond
>
> P.S. I'm simulating a TIA and need the nominal delay to
> check boundary conditions between the CPU Phase2, which
> strobes latches, and the divide-by-four clock, which runs
> the TIA circuits.
>
> --
> Democracy: The triumph of popularity over principle.
> --
> http://www.crbond.com
>
>
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