Re: [stella] Supercharger internals...

Subject: Re: [stella] Supercharger internals...
From: bwmott@xxxxxxxxxxxx
Date: Fri, 16 May 1997 14:40:32 -0400 (EDT)
> All the dicussions of the Supercharger have been good so far, but what happens here:
> F000  ldx #$3f      
> F002  cmp $f000,x   ;Write data = $3f 
> F005  NOP           
> F006  lda $ff7b     ;Write $3f to $f7b
> Wouldn't the SC see the opcode fetch from address F002 as Write data = $02 and the start of a ram write?

Humm... good question..  I'd say it works like this:

  cycle    action
   0       load opcode for ldx from location f000 
           write value is set to 00 (since we are accessing f000)
   1       load operand from f001 (3f)

   2       load opcode from f002 for cmp
   3       load low byte 00 from f003
   4       load high byte f0 from f004, add x to low byte
   5       load operand from f03f
   6       load opcode from f005 for nop
   7       do something but nothing ...

So I would say a poke(f03f,00) at cycle 5 or poke(f005,00) at cycle 6

However, this is assuming that once a poke write value is selected 
(i.e. an access from f000 to f0ff) other reads in f000 to f0ff do NOT 
select a new poke value.  If they did then the poke would be delayed 
until no more accesses to f000 to f0ff occur within 5 or 6 cycles.

What does everyone else think?


P.S. I don't have my cycle table handy so I might be off on these...

Bradford Mott (bwmott@xxxxxxxxxxxx)        Computer Science Department           North Carolina State University

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