Re: [stella] TIA latch timing

Subject: Re: [stella] TIA latch timing
From: Kevin Horton <khorton@xxxxxxxxxxx>
Date: Tue, 16 Oct 2001 23:22:13 -0500
At 15:53 10/16/01 -0400, you wrote:

On Tue, 16 Oct 2001, Eric Ball/Markham/IBM wrote:

> Is there a list somewhere which indicates the number of cycles after WSYNC
> when each TIA register is latched?  e.g. I believe the playfield registers
> are latched on color cycles 68 and 148 (left edge and middle of screen), so
> any updates to those registers need to be completed by CPU cycle 22 and 49.
> Also, are any registers not latched, so can only be updated during

Disclaimer: This is based on observed behavior, not actual knowledge of how
the hardware works...

I'm not sure they're latched, in the way you mean... if you change a TIA
register (PF0, say) while it's in the middle of being displayed, you will
actually see part of the old data and part of the new data.

I've looked over the schematic for how the PF operates, and it is really quite cute.

They used 2 20 bit shift registers in parallel, each "pointing" opposite directions. This allows for both normal and reflected playfields. What happens is, at the start of the scanline, a 1 is shifted into the first bit of a shift register.

Which register it goes in is determined by the reflect PF bit's setting. This bit then gets shifted through all 20 playfield bits in order, selecting the desired bit that gets displayed. If one were fast enough, he could make a 64 pixel resolution (or higher) playfield by writing in new data. Of course a stock 2600 cannot do this since the 6507 isn't fast enough. A PIC on a cart might be, though :-)

If this approach were tried, the colour regs could be written in real time in synch with the display to achieve a higher effective resolution using the whole 2600's palette.

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