Re: [stella] Midified VCS...

Subject: Re: [stella] Midified VCS...
From: Oliver Achten <achten@xxxxxx>
Date: Wed, 21 Nov 2001 15:50:16 +0100 (MET)
> On Tue, 20 Nov 2001, Glenn Saunders wrote:
> > >it does not seem to be that complex.
> >
> > The TIA chip has approximately 10,000 gates.

Wasn't it said to have about 5000 gates? Can't imagine that it has nearly
three times as many gates as the 6502 (considering the simplicity of the
design). You yould also simplyfy it by abadoning the old CVBS logic in favour of
having an rgb output (which would be much simpler).

> I'm spending about 10-15 hours a week on this project.  (Whoa!  Did
> anyone hear that?  Chris is spending more than 5 minutes a week on
> an Atari project!!!)  The good news here is that because I know what
> one section is doing, it's a lot easier to do the next section.
> The "5 pages of schematics" thing is kinda misleading.  Because those
> 5 pages consist of cell schematics that are then copied X,Y, or Z times
> as tiny little "black boxes".  And they consist, in part, of circuitry
> that
> you can't do in an FPGA without wasting gates.  And they consist, in part,
> of circuitry that you can't do in an FPGA at all.  And I've found one
> place where it looks like the ESD device is actually part of the
> functionality.  YUCK!

Again, what kind of logic do they use? To what level of abstraction are the
schematics drawn?
> I'm starting to think laying out an ASIC would be easier than doing it
> in VHDL.  I dunno.  But the good news is that I'm on target to start
> drawing pictures with this thing in late January or February.  Woohoo!

I hope you'll be succesful and that you will be in the right mood to write a
nice documentation about it....  ;-)

Are there any chances for a person not living in the states to have the



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