[stella] Reverse engineering the TIA (Was: Midified VCS...)

Subject: [stella] Reverse engineering the TIA (Was: Midified VCS...)
From: Oliver Achten <achten@xxxxxx>
Date: Thu, 6 Dec 2001 11:20:29 +0100 (MET)
Hello Mark!

I intend to redesign it using 74xx IC's (don't laugh...) . Preferably

Well, i looked at the counters, and they indeed consist of 6 self-feedbacked
shift registers, driven by a two phase clock , using some kind of wired-and
logic to decode various states. Fortunately, J. Miner wrote at the H-Sync
counter, which number causes some kind of action (H-SYNC start, etc.) The H-SYNC
counter is clocked 1/4 the clock of the master clock (3.58Mhz). Once I
figured out in what order it counts, this counter could be replaced by a standard
binary counter, since it really is not important in what order the H-Sync
counter counts (as long as your supply logic decodes the same states...).
Unfortunately, this is not valid for the player counters (because of the

The bus logic and sync decoding are not really a problem to do in TTL. The
Playfield registers are tricky. Could be replaced by latches and a flip-flop
chain, which is logically anded with the outputs of the latches.

The H-Move counters... Any idea? Well... Lets go to the next sheet...  ;-)

Sheet 2 consist mainly of the Bus drivers, the collision detection, and the
address decoding. The adress decoding consist again of primitive wired and
logic. TO do it in an FPGA, you'll have to convert it to real AND gates (which
will significantly increase the gate count). I intend to use 4 plain 74154 4
to 16 address decoders... (yuck).

The next 2 sheets consists of the player-missile-ball, etc logic. 

In the last sheet, there are 4 7-bit registers for the color data. Above is
the priority logic, which selects the color register. My prototype will have
the color phase delay logic replaced by two PROMS, where the colors are
hardcoded (as i said).

Well, thats how far i've gotten until today....



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