Hello there,
yesterday I mentioned a text, that explains the TIA sound hardware. The
file can be found in Ron Fries' TIASND10.ZIP, a TIA sound emulator engine.
I have included the relevant parts here and hope it helps finding a frequency
table.
Thanks, Eckhard Stolberg
==============================================================================
TIASOUND.C - TIA SOUND EMULATION V1.0
=====================================
As I'm sure you've already discovered, the Stella manual isn't always
correct. My observations show what I believe to be several discrepancies
in the description of the distortions. Of course, I could be wrong on a few
of these, so if some of the games don't sound right, please let me know
which ones. If possible, it would be best if you could send me a wave file
of what it is supposed to sound like, preferably at 44 KHz. Only a few
seconds should be necessary.
TIA AUDIO CIRCUITRY
===================
THE HARDWARE
------------
In general, the sound hardware can be described as follows:
Selecting the Clock Modifier - Bits D0 and D1
---------------------------------------------
Bits D0 and D1 select the output clock modifier:
D1 D0
-------
0 0 - direct clock (pure)
0 1 - direct clock (pure)
1 0 - divide by 31
1 1 - 5-bit polynomial
The 'divide by 31' isn't simply the input clock divided by 31. It is, in
essence, a 5-bit polynomial with only two bits set. The resulting square
wave actually has a 13:18 ratio. This may be implemented in the hardware
as a pair of traps on a 5-bit counter.
Selecting the Source Pattern - Bits D2 and D3
---------------------------------------------
Bits D2 and D3 select the source to be clocked:
D3 D2
-------
0 0 - 4-bit polynomial
0 1 - pure (Q')
1 0 - 5-bit polynomial
1 1 - pure (Q')
The 'pure' tones are generated by toggling the output. Whenever a clock
tick is received, the output will change states. I've used the notation Q'
to indicate the 'logical NOT of the last output'. Note that since the output
toggles, this can be thought of as a divide by 2 since the output frequency
will be half of the input frequency. This is only true for the pure tones.
Selecting the Source Clock - Bits D2 and D3
-------------------------------------------
When bits D2 and D3 are both set, it affects the source clock. I believe
the '30KHz' clock is actually the 3.58MHz clock divided by 114. When bits
D2 and D3 are set, the input source is switched to the 1.19MHz clock, so the
'30KHz' source clock is reduced to approximately 10KHz.
Exceptions - Selecting No Output or the 9-bit Polynomial
--------------------------------------------------------
There are two exceptions that occur when bits D0-D2 are all 0. If AUDC is
zero (0000), then I believe the output is set equal to the volume. If AUDC is
equal to 8 (1000), the 9-bit polynomial is selected as the source to be
clocked.
Updated Detailed Functions for AUDC
-----------------------------------
>From my observations, I would describe the distortion selections as follows:
HEX D3 D2 D1 D0 Clock Source Clock Modifier Source Pattern
--- ------------- -------------- ---------------- ----------------
0 0 0 0 0 3.58 MHz/114 -> none (pure) -> none
1 0 0 0 1 3.58 MHz/114 -> none (pure) -> 4-bit poly
2 0 0 1 0 3.58 MHz/114 -> divide by 31 -> 4-bit poly
3 0 0 1 1 3.58 MHz/114 -> 5-bit poly -> 4-bit poly
4 0 1 0 0 3.58 MHz/114 -> none (pure) -> pure (~Q)
5 0 1 0 1 3.58 MHz/114 -> none (pure) -> pure (~Q)
6 0 1 1 0 3.58 MHz/114 -> divide by 31 -> pure (~Q)
7 0 1 1 1 3.58 MHz/114 -> 5-bit poly -> pure (~Q)
8 1 0 0 0 3.58 MHz/114 -> none (pure) -> 9-bit poly
9 1 0 0 1 3.58 MHz/114 -> none (pure) -> 5-bit poly
A 1 0 1 0 3.58 MHz/114 -> divide by 31 -> 5-bit poly
B 1 0 1 1 3.58 MHz/114 -> 5-bit poly -> 5-bit poly
C 1 1 0 0 1.19 MHz/114 -> none (pure) -> pure (~Q)
D 1 1 0 1 1.19 MHz/114 -> none (pure) -> pure (~Q)
E 1 1 1 0 1.19 MHz/114 -> divide by 31 -> pure (~Q)
F 1 1 1 1 1.19 MHz/114 -> 5-bit poly -> pure (~Q)
For the most part, this follows the Stella manual, but there are a few
differences. Probably the most notable are hex entries 'A' and 'B', which
are listed in the Stella manual as 'div 31: pure tone' and 'set last 4 bits
to 1'.
On entries 'A' and 'B', both the data source and the clock have the same
number of entries (31). Because of this, they will always align in the
same way. Entry 'A' will then reduce to a pure 'div by 31' output which
is identical to entry '6'. On 'B', both the source and the clock align
in such a way that the output will always be 1.
THE POLYNOMIALS
---------------
The 4-bit, 5-bit, and 9-bit polynomials are essentially tables containing
a random series of bits (they are implemented in hardware as shift
registers). Because the tables are fixed in length, the 'random' pattern
will repeat periodically.
The size of the table is described by its name. The actual size of the
table is 2^x - 1, where x is either the 4, 5 or 9. The 4-bit polynomial
has 15 entries, the 5-bit polynomial has 31 entries, and the 9-bit
polynomial has 511 entries.
I've performed some analysis on the output of the actual Atari 2600, and
believe I have the actual 4-bit and 5-bit polynomials used by the Atari.
These have been encoded as byte arrays in my routines. For the 9-bit
polynomial, I use a random number generator which should produce
approximately the same results.
THE CLOCK
---------
I believe the input clock for the audio is a division of the main system
clock. With this assumption, I determined that the input clock for the
audio is equal to the 3.58MHz system clock divided by 114. Note that this
produces an actual audio clock of 31.4 KHz. This value closely matches the
frequencies I recorded from my unit. The Stella manual describes the Audio
Clock as approximately 30KHz, which I suppose is correct if you consider 5%
to be approximate.
If both bits D2 and D3 of the AUDC register are set, I believe the TIA chip
uses the 1.19MHz clock for the base audio clock instead of the 3.58MHz.
This, of course, produces the 'divide by 3' functionality described in the
Stella manual.
TiaSound is Copyright(c) 1996 by Ron Fries
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