RE: [stella] Formats (64K Flat Model??)

Subject: RE: [stella] Formats (64K Flat Model??)
From: Erik Mooney <emooney@xxxxxxxxxxxxxxxx>
Date: Tue, 5 May 1998 09:56:36 -0400 (EDT)
> Well there's around 250 binaries.  One for each instruction except for
> JAM's.  They're only 1K or so each, but each one would need to be
> disassembled, re-org'd and reassembled, not to mention modified to do
> something sensible to the screen on the 2600.  So far I haven't had much

Well, sending stuff to the 2600's screen could be as simple as a six-digit
score routine, I think... and once working, it can be used for all the
modules.  If you can get a disassembler to work, it doesn't sound all that
difficult.

> > It wouldn't be a flat 64k space, though - the TIA and RIOT wouldn't know
> > to ignore accesses to $2000, $4000, etc - because those upper 3 address
> > bits are *physically not present* inside the console.  The best you could
> > do is stripes of 4k each, for 32k total...  or exactly what we get in the
> > Tigervision 32k bankswitch method.
> 
> Oops, didn't think of that.  But it would still be easier to program for.
> This is one bank-switch scheme that the assembler

Aww, c'mon, get into the classic spirit and write code in 4k chunks :)

> The parasite CPU would still need to watch the host CPU do something on the
> bus every once and a while to keep synchronized.  You could stay pretty
> close by running at a clock frequency that's a multiple of the TIA
> frequency, but there would still be some slippage.

"Parasite"?  More of a symbiont ;)  The point is the fast CPU doesn't need
to be synced to the 6507.  It just holds the 6507's data lines to the
opcode for NOP until it wants the 6507 to do something... then it delays
the appropriate amount of time between parts of the 6507 instruction.

> This looks pretty clever actually, force feeding instructions to the host on
> the fly.  But it would probably take a bit more horsepower than even I had
> in mind.  Unless you had some dual-ported RAM or DMA support on the
> microcontroller.  I was thinking one instruction per TIA clock.  Chips are
> cheap.  Around 5 bucks a pop in quantity with RAM and one-time programmable
> EPROM built in.  But maybe someday...  Maybe next year!

That's why I was vague on the "6507 interface" part, cause I really dunno
how to do it :)
 
> > And you'd need either some way to reverse the interface, so
> > the fast CPU could read controlller and switch input from the TIA, or just
> > plug the controllers into the cart, with an extra I/O chip.
> 
> Just feed it the instructions to read the switch inputs, and watch the data
> go by on the bus.

Er, what bus?  The new CPU has its own private memory bus... where are we
gonna connect the 6507 data bus to the new CPU?


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