Subject: Re: [stella] TIA latch timing|
From: Kevin Horton <khorton@xxxxxxxxxxx>
Date: Tue, 16 Oct 2001 23:22:13 -0500
On Tue, 16 Oct 2001, Eric Ball/Markham/IBM wrote:
> Is there a list somewhere which indicates the number of cycles after WSYNC > when each TIA register is latched? e.g. I believe the playfield registers > are latched on color cycles 68 and 148 (left edge and middle of screen), so > any updates to those registers need to be completed by CPU cycle 22 and 49. > Also, are any registers not latched, so can only be updated during > HSYNC/VSYNC/VBLANK? >
Disclaimer: This is based on observed behavior, not actual knowledge of how the hardware works...
I'm not sure they're latched, in the way you mean... if you change a TIA register (PF0, say) while it's in the middle of being displayed, you will actually see part of the old data and part of the new data.
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