Subject: Re: [stella] Critical CPU/TIA Timing From: "Andrew Davie" <atari2600@xxxxxxxxxxxxx> Date: Sun, 14 Sep 2003 08:55:38 +1000 |
Session 18 of my Programming the 2600 Tutorials contain a detailed timing diagram for CPU writes to TIA for PF updates. Here's the link to that session... http://www.atariage.com/forums/viewtopic.php?t=29326 Cheers A ----- Original Message ----- From: "C. Bond" <cbond@xxxxxxxxxxxxx> To: <stella@xxxxxxxxxxx> Sent: Sunday, September 14, 2003 1:10 AM Subject: [stella] Critical CPU/TIA Timing > Has anyone put together a timing chart documenting the critical timing > issues in CPU writes to the TIA? For example, it seems that programmers > frequently have to set up count loops or use a series of NOPs to > experiment with timing until the get what they are looking for. It would > > be much easier if the timing issues where documented once and for all. > (Of course, the major timing relationships are well-documented in the > TIA Hardware Manual -- but not the fine details.) > > A typical problem is to determine the last CPU cycle at which it is > 'safe' to update PF0 during HBLANK so the current line accepts the > change. Since CPU writes occur during phase 2 of the CPU clock on the > last cycle of the instruction, a STA Z.P. which starts on CPU cycle 20 > (pixel clock 60) should execute near the end of CPU cycle 22 (pixel > clock (pixel clock 64? - 65?). Then there is the time required for the > TIA to transfer the PF0 register to the parallel to serial logic and > begin piping it to the composite video. > > It would seem that the timing could be determined and documented > somewhere to reduce the amount of testing many programmers do. Similar > questions arise in determining what is the last CPU cycle where it is > safe to issue a WSYNC and have it honored on the current line (71?, > 72?,...)? > > CPU 1 2 3 4 5 > _____ _____ _____ _____ _____ > Phase1 _/ \_____/ \_____/ \_____/ \_____/ \__ > _ _____ _____ _____ _____ __ > Phase2 \_____/ \_____/ \_____/ \_____/ \_____/ > _ _ _ _ _ _ _ _ _ _ _ _ _ _ > CLOCK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ > > STA | OP CODE | ADDRESS |WRITE /////| OP CODE _ _ _ _ > Z.P | FETCH | FETCH |DATA /////| FETCH > ^^^^^ > Is it possible, using this kind of timing chart, to reliably identify > the exact pixel clock at which the TIA can handle the new data? Again, > the two obvious cases are in determining the last reliable point at > which a WSYNC can be issued or a Player, Missile, Ball, Playfield change > > would work? > > Thanks for any input, pointers, etc.... > > -- > http://www.crbond.com > > > -------------------------------------------------------------------------- -------------------- > Archives (includes files) at http://www.biglist.com/lists/stella/archives/ > Unsub & more at http://www.biglist.com/lists/stella/ > > ---------------------------------------------------------------------------------------------- Archives (includes files) at http://www.biglist.com/lists/stella/archives/ Unsub & more at http://www.biglist.com/lists/stella/
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