The FET is a pass gate. When the FET is turned off, the inverter input
sees what was placed there the last time the FET was turned on. But this
is only temporary. The input capacitance will hold the value, but charge
will slowly leak away and the value will become corrupt. In this case, it's
ok because the input to the FET is a clock, and it will refresh the inverter's
input node before it gets corrupted. This is the same way DRAM works, BTW.
-Chris
On Tue, 16 Sep 2003, Adam Wozniak wrote:
> On Tue, 16 Sep 2003, Dan Boris wrote:
> > Those are blocks that are defined elesewhere. In the upper right corner
> > of page one you will see the circuit diagram for that type of block
> > labeled D1.
>
> The asterix next to the FET is a little odd. If the gate on the FET
> is held low, do the inverters see a logic 1 or logic 0 on their inputs?
>
> i.e.
> is this:
>
> b
> |
> = |\
> a ----| |-----| >o----- out
> |/
> FET inverter
>
> simply a nand gate?
>
> --
> adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam/pgp.html
> Will code for food. http://cuddlepuddle.org/~adam/resume.html
> "The dinosaurs are not around today because they did not have a space program."
> -- Arthur C. Clarke
>
> ----------------------------------------------------------------------------------------------
> Archives (includes files) at http://www.biglist.com/lists/stella/archives/
> Unsub & more at http://www.biglist.com/lists/stella/
>
>
----------------------------------------------------------------------------------------------
Archives (includes files) at http://www.biglist.com/lists/stella/archives/
Unsub & more at http://www.biglist.com/lists/stella/
