Subject: Re: [stella] more tia schematic questions From: Adam Wozniak <adam@xxxxxxxxxxxxxxxx> Date: Wed, 27 Oct 2004 13:17:31 -0700 (PDT) |
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On Wed, 27 Oct 2004, Chris Wilkson wrote: > That seems reasonable. Though strictly speaking you should always cover > all your input possibilities. I.e. with "else" clauses in "if" statements > and "others" in "case" statements, etc. I think processes (doesn't your > "if" statement have to be inside a process?) imply flops, so you might get > away with it in this case, but it's mildly deprecated. > > This is just a D-Latch. (thus the "L" designation). Depending on which > design software you're using, adding a signal "d" in your code might use > extra hardware when compiled. You can get the same functionality with > > if p1 = '1' then > p3 <= p5; > else p3 <= p3; > end if; > > p4 <= not p5; Don't you mean p4 <= not p3; ? I'm sure there's a concurrent version of the if... something like p3 <= p5 when (p1 = '1') else p3; p4 <= not p3; - -- that look right? > If you really really want an all VHDL > design, you can then compile your single D-latch schematic into VHDL > and steal the code from yourself, for yourself. :) I didn't think a schematic capture in a proprietary tool was appropriate for a GPL project. - -- adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam KG6GZR http://cuddlepuddle.org/~adam/resume.html "Did he get the girl? Oh, yeah. Why do you think he is drinking?" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.1 (GNU/Linux) iD8DBQFBgAJYyvXf5Z0z5zERAkHDAKC0v7HP1B4lTCmpajk9q4HCUQMRlwCdGMOx 6SqbRA+t+SLZDxxeTtvNlqw= =efnn -----END PGP SIGNATURE-----
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