Re: [stella] Supercharger internals...

Subject: Re: [stella] Supercharger internals...
From: danboris@xxxxxxxxxxxxxxxx (Dan Boris)
Date: Thu, 15 May 1997 08:21:01 -0400
> Hi Everyone!

> I'm working on version 0.7 of Stella, an atari 2600 emulator, and have
> been integrating some code written by Christopher Salomon for
> Supercharger support into this version.  I've gotten his code
> working and I'm able to play most of the Supercharger games, however,
> I'm still a little puzzled about the Supercharger's hardware.

	I was thinking about this same problem when I was trying to add Supercharger suport to V2600 (I only had a little success). I was never able to come up with a completely reasonable explenation of how the Supercharger works at the hardware level, but here are some observations that may help put the puzzle together.

1. The supercharger cannot actually count processor cycles since the are no signals going to the cart connector that would allow this (like PH2 clock). I could concievably have a free running timer built in that runs the same speed as the processor clock.

2. I know the RAM write works when the code is running from the cart ROM, but I am not sure if it works running from the VCS RAM. This would be an interesting thing for someone to try. If it did not work from RAM then it is possible that the SC is counting cart memory accesses.

3. Something that enters into this (and may be the answer to the problem) is the Write Pulse Delay setting in bits D5..D7 of the control byte. I believe this determins the maximum delay between doing the data write and doing the address write. It would seem to be mesasured in processor cycles since it can be a value fro 0 to 7:

  F800  ldx #$3f      
  F802  cmp $f000,x   (data write is on last cycle of instruction) 
  F805  NOP           (1 cycle)
  F806  lda $ff7b     (4 cycles, address write is on the last cycle)

So the write to SC ram happens on the 5th cycle after the data was written, and taking out the NOP would reduce it to 4. Both of these are right around the middle of the range of the write pulse delay.

Also, if you look at the source code for the Supercharger BIOS rom, you can see that it goes through a rather extensive process to determine the optimum setting for Write Pulse Delay which would support the idea that there is a free running clock in the Supercharger and the Write Pulse Delay needs to be adjusted to compensate for any differences between this clock and the processor clock.

Even with all this information I still do not see how the Supercharger differentiats between opcode accesses and data accesses. If anyone has can put this info together into a logical explenation of how the Supercharger works I would love to hear it. 

						Dan Boris

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