>2. I know the RAM write works when the code is running from the cart ROM,
but I am not sure if it works running from the VCS RAM. This would be an
interesting thing for someone to try. If it did not work from RAM then it is
possible that the SC is counting cart memory accesses.
>
I have just written a little test program that does SC writing with code
executed in the VCS RAM and it works. So that does not semm to be the
explanation.
>3. Something that enters into this (and may be the answer to the problem)
is the Write Pulse Delay setting in bits D5..D7 of the control byte. I
believe this determins the maximum delay between doing the data write and
doing the address write. It would seem to be mesasured in processor cycles
since it can be a value fro 0 to 7:
>
> F800 ldx #$3f
> F802 cmp $f000,x (data write is on last cycle of instruction)
> F805 NOP (1 cycle)
> F806 lda $ff7b (4 cycles, address write is on the last cycle)
>
>So the write to SC ram happens on the 5th cycle after the data was written,
and taking out the NOP would reduce it to 4. Both of these are right around
the middle of the range of the write pulse delay.
>
Don't NOPs take 2 cycles?
What is strange is, that in all my programs I have to use a NOP in the
SC writing routine like
LDX #$1d
CMP $F000,X
NOP
CMP $FFF8
or the program would crash, because it overwrites some part of the code.
But Bob's Etch program, for example, runs perfectly on my system, although
it doesn't have the NOPs.
>Also, if you look at the source code for the Supercharger BIOS rom, you can
see that it goes through a rather extensive process to determine the optimum
setting for Write Pulse Delay which would support the idea that there is a
free running clock in the Supercharger and the Write Pulse Delay needs to be
adjusted to compensate for any differences between this clock and the
processor clock.
>
Since you have already dumped the SC BIOS, would it be possible, that you
send me a copy or post it here?
Ciao, Eckhard Stolberg
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