Re: [stella] Idea for Scrolling Maze Engine.

Subject: Re: [stella] Idea for Scrolling Maze Engine.
From: emooney@xxxxxxxxxxxxxxxx (Erik Mooney)
Date: Sun, 07 Feb 1999 22:40:54 GMT
>Wow!  It's so great to see the 6502(7) discussed!  It feels like my small
>isolated programmer bubble has expanded into a medium size isolated
>programmer bubble...but enough small talk.  Being an eager new convert
>to the land of 2600 programming and the TIA, I've ingested a few of the
>major documents and decided to write a small kernal to see if I have
>any clue how any of this works.  Before I go on...

Well, the rule of 2600 programming is that if it works, it's good, no
matter how cluttered or ugly the code is :)

>Assume an assymetrical playfield, which will mean 40 blocks of horizontal
>resolution (4 color clocks each).

If you can't optimize your kernel enough, I'd suggest reducing the scope
of this to 36 blocks instead of 40, leaving out the first PF0... this'd
save you a significant amount of calculations, maybe enough to get the
kernel to fit within two scanlines.

>Here's how it works....for any PF register or its right side equivalent,
>use the "shift" and two of the maze flags as an index.  Load the byte from the
>table and store it to the register...some registers need to load two bytes
>from the table and ORA them together for reasons that are easier to draw
>than explain.  All this depends on the "coincidence" that the boxes are 8
>bits wide...this means that most registers are only affected by two drawing
>flags, some by three, but we always know exactly which are affected by what.
>
>PF0 (first 4 blocks) affected by flags A and B
>PF1 (next 8) flags A B and C
>PF2 (next 8) flags B C and D
>altPF0 C and D
>altPF1 D and E
>altPF2 E and F
>
>This can be cleaned up if you find a scheme so that no register is affected
>by more than two flags.  (Or also, you could create a lookup table that uses
>three drawing flags in it's index.)

You can't.  The reason is that the 4-bit PF0s mess up the 8-8 patterns,
so one or the other PF1 has to catch the other 4 bits that PF0 couldn't
hold and then two 8-wide flags of its own.

>sta altPF0     (3) [72] don't copy until correct time, or something like that
>lda altPF1DC,Y (4) [76] read table
>^^^^^^^^^this is aproximately where we reach scanline #2??^^^^^^

This is exactly where scanline #2 begins.  You do not actually need to do
a STA WSYNC if you're sure that the above code is always 76 cycles (no
page boundary accesses.)

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