Ok, so building from your suggestions here's my second attempt:
Use PF1 and PF2 in reflection mode, which yields 32 pixels, IF you can
swap PF2 at the right moment, which I discuss below. PF0 is never updated.
use maze flags A thru E, with A as LSB ( E D C B A )
The flag-to-pixel looks like this: (R means "Righthand")
32 pixels --->
|PF1 ||PF2 ||PF2R ||PF1R |
AABBBBBBBBCCCCCCCCDDDDDDDDEEEEEE
with a shift of 2 for illustration.
There is some nice symmetry; each register is affected by exactly 2 flags.
We only need two lookup tables.
PF1 (BA) table1
PF2 (CB) table2
PF2R(DC) table1
PF1R(ED) table2
Remember all the work I did last time combining the shift with the flags
for a table index? It really only needs to be done once per frame, using
zero page pointers.
I setup "table1ptr" to table1 + (shift*4)
and "table2ptr" to table2 + (shift*4)
Here's the only problem. We need to perfectly time the swap from PF2L to PF2R.
We want to update just as the scanline hits the center of the screen.
If we swap too early, some data from PF2R is reflected to the left by early
drawing. If we swap too late, some of PF2L is reflected to the right.
I would suggest that reflecting some or all of bit 7 is tolerable IF you can
repeat the phenomena for each scanline (which means careful timing).
Here's how I see it (corrections welcome of course)
Since my code is two scanlines long, I'm going to look at the SECOND
middle crossing and ignore the first for now.
start our clocks at time 0, 3 color clocks for every cpu clock.
color CPU
start 0 0
end line1 228 76
hblank +68
296
middle +80
376 125.3 (376/3)
which means our goal is to affect a swap right smack on top of cpu clock
125, or color clock 375, one color clock early, giving a 1/4 pixel reflection.
If we do it on cpu 124 (color 372) that's 4 colors early, thusly 1 pixel
reflection.
If we do it on cpu 126 (color 378) thats 2 colors late for 2/4 reflection.
sta PF2 takes 3 cpu cycles (unless the TIA slows this down somehow)
I could look it up, but I'm going to guess that the first two cycles are used
for the address mode, and the last cycle is used to write the data
(or perhaps the last cycle increments the PC). So the big question is when
does sta PF2 have to start?
cpuclock121 nop (burn clock 121 and 122 for example)
sta PF2 (use clock 123, use clock 124, write on 125)
Is the TIA instantaneous in using new register data, or can we get away with
writing to PF2 a little early (for example on cpu clock 124)??
Well that question is probably a thread unto itself....
Here's my new code, which ignores the need to draw scanline1, but which
buffers the data needed to draw scanline2. It does a little bit less (32
pixels and not 40), but it runs faster.
ldx maze (3) [ 3] get our maze flags (E D C B A)
and use X Register to hold them
txa (2) [ 5]
and #3 (2) [ 7] mask for flags B and A
tay (2) [ 9] use Y as a 0-3 index into our mini-table.
lda (t1ptr),Y (5) [14] t1ptr points to table1 + shift*4
sta tempPF1L (3) [17] buffer the data until drawing.
txa (2) [19] maze flags
lsr (2) [21] prepare C and B, drop A
tax (2) [23] save the shift to save time later
and #3 (2) [25] mask for C and B
tay (2) [27]
lda (t2ptr),Y (5) [32] t2ptr is table2 + shift*4
sta tempPF2L (3) [35]
txa (2) [37]
lsr (2) [39]
tax (2) [41]
and #3 (2) [43] flags D and C
tay (2) [45]
lda (t1ptr),Y (5) [50]
sta tempPF2R (3) [53]
txa (2) [55]
lsr (2) [57]
and #3 (2) [59] flags E and D
tay (2) [61]
lda (t2ptr),Y (5) [66]
sta tempPF1R (3) [69]
... do other stuff here
lda tempPF1L (3) [72]
sta PF1 (3) [75] draw from buffer
... other stuff
lda tempPF2L (3) [78]
sta PF2 (3) [81]
...
lda tempPF2R (3) [84]
sta PF2 (3) [87] <----timing crucial
...
lda tempPF1R (3) [90]
sta PF1 (3) [93]
...
93 < 130 means version 2 is faster Yay!
-Andrew Schwerin
schwerin@xxxxxxxx
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