Mark De Smet wrangled the electrons to say:
>
> I must say, I am very impressed with how far you have taken this. The PC
> GUI program is quite impressive, and could make for a very nice product.
> You don't think that you would be able to sell it then? Besides that
> humorous email, have you gotten many/any serious requests for purchase,
> even at the >100$ price tag?
Thanks. Yeah, I've received a few emails here and there. Certainly not a
flood. I'm not sure how widely known it is.
> How would you discribe your overall architecture? By this I am asking
> about a high level block.
Basically I have one CPLD handling bank switching and one handling the
parallel port. All of the Atari's address bus connects to the CPLD, as does
most of the SRAM's address bus (save for a few bits from the top end - I'd
have included more if I had any more pins). The parallel port CPLD provides
a number of latch structures that allow latching address and data and
twiddling the SRAM's write signal. There are some interconnections between
the CPLDs so the parallel port CPLD can configure the bankswitch mode of the
bankswitch CPLD.
Forgive the rough outline, it's been a few months since I designed it and I
haven't stared at the schematics in a while..
> --------------
> Atari Addr----->| CPLD/ | ------------------
> Atari Data<---->| FPGA |<-------->| PC interface |
> -------------- ------------------
> ^ |
> |(Data) |(Addr)
> V V
> -------------
> | RAM |
> -------------
This is a really good way to go about it. You nailed the major benefit:
sheer flexibility. I believe Xilinx does make a part big enough to do this.
If I do another version, I will probably approach it this way, rather than
segmented. I had to segment the design because I was working with 44-pin
parts.. My original intent was basically what you describe here.
> Do you really support Pitfall II? I note that you have it labeled as
> simple F8 switching, which it is not.(It is switching, i'd believe F8, but
No; that was a mistake. I apologize for the error. Oversight from the
database conversion.
> addressing) in your switching chip? I don't see a crystal, does the CPLD
> have one on it, or do you generate it from the Data/Addr lines?
The CPLDs don't need a clock inherently.
> How do you run your parallel port logic? Crystal, clock in CPLD, or does
> it run off of a parallel port clock pin?
Latch structures, no state machines. Nothing needs to be driven by a clock.
> The last(so far only) RAM cart I made(a long while back), was only a 4k
> version, and had no PLD. Further it supported the printer protocal. By
> this I mean that you could load it with the simple DOS command:
>
> copy /b filename.bin lpt1
>
> (/b to force a binary copy, it will fail otherwise). I had used the
> strobe line to clock in the data and increment address counters.
I remember reading about that after my friend and I designed the first
version a couple years ago.. That was a pretty nifty way of approaching it.
Our first version used custom software as well (though it was only DOS
command-line based).
> Did you implement extended hardware features that programmers could use?
> For instance, like being able to write data out of the cart to the
> parallel port interface for communcation w/ the PC? Does your
> architecture allow this?
With my current architecture this is not possible .. or at least I can't
figure out how it would be. There's bus contention on the 8 data bits
because I wasn't able to 'abstract' (for lack of a better term) those
through a CPLD - I ran out of pins. Instead I high-Z the CPLD that drives
the lines when the 2600 is playing. This is something I really want to fix
in the next spin, if there is one.
> Do you have much space left inside your CPLD's, or have you pretty much
> maxed them with the switching/loading logic?
The bankswitch chip is pretty near full. It's a 72 macrocell version of the
part. I think I can get a 144 macrocell part in the same package, but I
can't remember at the moment. I know if I step up to a higher pin-count
package I can get much higher macrocell counts.
I had started to write E0 bankswitching (Parker), and I remember having to
temporarily disable one or two of the other types to get it to fit. I
wasn't able to get it to work in the hour or so of experimenting I did, so I
moved on to some other things.. One of these days I want to get back to
that...
> Are you still working on this?
At the minute, no .. I tend to keep myself very busy with a variety of
projects. I do, however, intend to come back to it.. So it's just on hold
until my interest level rises again.
I've considered selling off four of the PC boards from the first run to
interested developers.. I'd probably have to include programmed CPLDs to
make them useful.. not to mention stuff most of the PCBs .. Something tells
me soldering surface mount 0402-sized ceramic chip caps is not something
people really want to be doing without the right equipment..
Who knows....
-S
--
Stephen S. Richardson The GweepCo Cooperative Network
prefect@xxxxxxxxx network access * technology vulturing
http://www.gweep.net/~prefect/ http://www.gweep.net/
--
Archives (includes files) at http://www.biglist.com/lists/stella/archives/
Unsub & more at http://www.biglist.com/lists/stella/
