Re: [stella] "Illegal" opcodes

Subject: Re: [stella] "Illegal" opcodes
From: Erik Mooney <emooney@xxxxxxxxxxxxxxxx>
Date: Sun, 18 Jun 2000 11:53:27 -0400
>Forgive my ignorance and curiousity, but who "officially" defined the
>instruction set?  Are these illegal opcodes lucky by-products that just
>happen to work when you use the right byte?  And then how were they

Being undocumented by the designers of the 6502 (and not present in
later versions of the 6502 architecture) is the only thing "illegal"
about them.  They are accidental, but I'd be fairly sure that the chip
designers did realize that they could be used.

In a nutshell, here's what happens:
The opcode for LDY is $AC, or 10101100 binary.
The opcode for LDA is $AD, or 10101101 binary.
The opcode for LDX is $AE, or 10101110 binary.

The first six bits, 101011, indicate a load instruction.  Then the last
two bits indicate the destination - if nothing is set, load the value
into Y; if the last bit is set, load it into A; if the second-lowest bit
is set, load it into X.

But what happens if we set the two lowest bits, making the opcode $AF,
in binary 10101111?  Well, that meets the conditions for both the "load
into A" and "load into X" cases, so the value is loaded into both of

At a gate level, it becomes easier to understand, for hardware techies
at least.  The 8-bit latches for the A and X registers are each
triggered to read from the bus by a single bit in the opcode.  Nobody
bothered to check the second-lowest bit for A's latch or the lowest bit
for X's latch - it's unnecessary, and adds to chip real estate and hence
manufacturing cost.  The neat dual-load capability.that results is just
a bonus, but the designers may well have noticed that was the result,
and not made an attempt to do anything else with the 10101111 opcode.
(It could easily have been used for one of the single-mode no-addressing
instructions like TAX or PHA.)

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