Subject: Re: [stella] Interlace From: Erik Mooney <emooney@xxxxxxxxxxxxxxxx> Date: Sun, 24 Sep 2000 19:30:24 -0400 |
>> In 2600 terms, you would enable VSYNC in the center (cycle 38) of scanline >> #263 (counting from 1) after you enabled it previously. Then you'd turn >> off VSYNC in the middle of scanline #266, and turn it on again at the >> beginning of scanline 526 (scanline 1 of the next 30Hz frame.) RSYNC >> isn't involved - there's no interruption or resetting to the horizontal >> timing to get a vertical offset for interlace. > >I think this would be a good thing to try. I would however add something >to that. If you don't add RSYNC, you will be screwed for trying to draw >anything during your kernal because you won't be able to use WSYNC. Who >here wants to do a kernal without WSYNC? I say this because if you used >WSYNC, it would release in the middle of the line instead of at the end. No, it wouldn't. Bad ASCII art follows: 1############################# 2############################# 3############################# 4----------------------------- 5----------------------------- ... 261--------------------------- 262--------------------------- 263------------############### 264########################### 265########################### 266############--------------- 267--------------------------- ... 525--------------------------- 1############################# That's what the VSYNC diagram looks like. What this does is move scanlines 267 through 525 _down_ by half a scanline-height, because VSYNC started a half-line late. WSYNC has no idea what VSYNC is doing, and it doesn't care. There is no interruption or resetting to the horizontal timing at all. WSYNC will _not_ trigger on the beginning of VSYNC on line 263, nor at the end of VSYNC on line 266 -- why would it? -- Archives (includes files) at http://www.biglist.com/lists/stella/archives/ Unsub & more at http://www.biglist.com/lists/stella/
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