Re: [stella] Warring Worms on real VCS

Subject: Re: [stella] Warring Worms on real VCS
From: "Thomas Jentzsch" <tjentzsch@xxxxxx>
Date: Tue, 16 Oct 2001 09:35:52 +0200
Roger Williams:
> Eckhard already posted that you're generating the wrong number of scan
> lines.  I suspect some bit of midscreen game or positioning logic is causing
> you to miss a WSYNC.  That's the kind of thing I'd look for first.

The problem is starting at the end of the overscan, where you are waiting for the timer. Sometimes you just get the correct line and sometimes not. Here is an extract from the trace of z26:

(the first column shows the row, the second the current cycle in that row)

Frame 1:
264  47  f224: ad 84 02 lda  INTIM   
264  51  f227: d0 fb    bne  f224    
264  53  f229: 60       rts          
264  59  f865: 4c 4a f5 jmp  f54a    
264  62  f54a: 20 0a f2 jsr  f20a    
264  68  f20a: a9 02    lda #02      
264  70  f20c: 85 02    sta  WSYNC   
265   0  f20e: 85 02    sta  WSYNC   
266   0  f210: 85 02    sta  WSYNC   
267   0  f212: 85 00    sta  VSYNC   
  1   3  f214: 85 02    sta  WSYNC   
  2   0  f216: 85 02    sta  WSYNC   
  3   0  f218: a9 2c    lda #2c      
  3   2  f21a: 8d 96 02 sta  TIM64T  
  3   6  f21d: a9 00    lda #00      
  3   8  f21f: 85 02    sta  WSYNC   
  4   0  f221: 85 00    sta  VSYNC  <- ends at line 4

Frame 2:
263  51  f224: ad 84 02 lda  INTIM   
263  55  f227: d0 fb    bne  f224    
263  57  f229: 60       rts          
263  63  f865: 4c 4a f5 jmp  f54a    
263  66  f54a: 20 0a f2 jsr  f20a    
263  72  f20a: a9 02    lda #02      
263  74  f20c: 85 02    sta  WSYNC <- this happens one cylce to late  
264  76  f20e: 85 02    sta  WSYNC (weird trace, should be 265 0)  
265  76  f210: 85 02    sta  WSYNC   
266  76  f212: 85 00    sta  VSYNC   
  2   3  f214: 85 02    sta  WSYNC   
  3   0  f216: 85 02    sta  WSYNC   
  4   0  f218: a9 2c    lda #2c      
  4   2  f21a: 8d 96 02 sta  TIM64T  
  4   6  f21d: a9 00    lda #00      
  4   8  f21f: 85 02    sta  WSYNC   
  5   0  f221: 85 00    sta  VSYNC <- ends at line 5

The problem occurs, because the timer-loop needs 5 cycles, and in your case this tolerance is to much and you are ending VSYNC one line to late.

To solve this problem you need to start the timer just some cycles earlier:

Change this code...:
f5dd: 
    sta  WSYNC   
    lda #8e      
    sta  COLUBK  
    lda #08      
    sta  TIM64T  

...into: 
f5dd: 
    sta  WSYNC   
    lda #08      
    sta  TIM64T  
    lda #8e      
    sta  COLUBK  

Now the timerloop finishes 5 cylces earlier. That should help.

BTW: Eckhard, the cycle counting is looking a bit weird, the 76 shoudn't be possible. Could it be a bug in the emulator?

Have fun!
Thomas
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