Re: [stella] FE, 3F, Bankswitching, and Data lines

Subject: Re: [stella] FE, 3F, Bankswitching, and Data lines
From: Chad Schell <gamer@xxxxxxxxxxx>
Date: Wed, 18 Dec 2002 10:54:59 -0800
The XC9500 series are CPLDs, not FPGAs. They're basically larger versions of PALs. Timing and routing are often much simpler than FPGAs.

What are you using to generate the timing for when the address lines and data lines are stable?


At 04:11 AM 12/18/2002, you wrote:
To late now, already done. I dont know Verilog or VHDL, I liked using Xilix's
schematics editor, all I had to do was draw my circuit and its done. Sure the
simple bankswitching could just be done with basic logic chip at RadioShack
but, I wanted to support all bank switching types. I am up to the XC95144,
which has a ton of gates, but not all are dedicated to bank switching. I also
want to work in Pitfall II and Starpath, maybe someday.

> I don't think you really need a full blown FPGA like the mentioned Xilinx
> XC9500 to do bank-switch emulation in hardware. Some of the simple schemes
> (F6, F8, FA) can easily be implemented using a cheap Programmable Gate Array
> like a PAL20V16. I haven't tried though, but you can try yourself. Get
> yourself some VHDL compiler and select a PAL20V16 or GAL20V16 as target
> architecture and check if your code can be synthesized in one of these.
> Shouldn't be too hard.
> With kind regards,
> Matthias
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============================================ Chad Schell

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