Thomas Jentzsch wrote:
> C. Bond wrote:
> >Has anyone put together a timing chart documenting the critical
> >timing issues in CPU writes to the TIA?
>
> For the PF writes check Andrews timing chart at AtariAge. The
> delay seems to be 2 pixel (or 2/3 CPU cycles).
>
> So get the pixel where the PF grtaphic starts subtract 2, divide
> the result by 3 and truncate it.
>
> >Similar questions arise in determining what is the last CPU cycle
> >where it is safe to issue a WSYNC and have it honored on the
> >current line (71?, >72?,...)?
>
> The write to WSYNC must *end* at cycle 76.
>
> Have fun!
> Thomas
I think you're right to focus on where the instruction execution ends, because that last cycle is
where the action takes place. If I understand your remark about WSYNC, a STA Z.P. (3 cycles)
should start at cycle 74, but a STA Z.P.,X should start at cycle 73. Correct?
--
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