Re: [stella] 6502 question (was INV+ ... )

[Christopher Tumber <christophertumber@xxxxxxxxxx>]

>I'm asking because I'm trying to do something crazy: hit
>RESP0 and RESP1 with fewer than 3 cycles difference. 


I dunno if this is exactly what you have in mind, but it seemed like an interesting exercise.

(It's a bunch of 11 pixel wide sprites)

Works fine on my Supercharger.


Chris...

	processor 6502
	include vcs.h




 SEG.U   variables
 org $80






    SEG     Bank0

    org $F000


Start:

      SEI  ; Disable interrupts, if there are any.
      CLD  ; Clear BCD math bit.

      LDX  #$FF
      TXS  ; Set stack to beginning.

      LDA #0
B1    STA 0,X
      DEX
      BPL B1




MainLoop
VerticalBlank  ;*********************** VERTICAL BLANK HANDLER



	LDA  #2
	STA  VSYNC ;Begin vertical sync.
	STA  WSYNC ; First line of VSYNC
	STA  WSYNC ; Second line of VSYNC.

	LDA  #43
	STA  TIM64T
	LDA  #0
;	STA  CXCLR
	STA  WSYNC ; Third line of VSYNC.
	STA  VSYNC ; (0)





      lda #0
      sta GRP0
      sta GRP1
      lda #$00
      sta COLUBK
      sta COLUPF
      lda #$0d
      sta COLUP0
      lda #$0d
      sta COLUP1
      lda #3
      sta NUSIZ0
      sta NUSIZ1


DrawScreen ;**************************** SCREEN DRAWING ROUTINES
      LDA INTIM
      BNE DrawScreen 
      STA WSYNC
      STA VBLANK  


      sta WSYNC
      sta WSYNC

      ldx #$ff
      txs
      jsr Trick
      jsr Trick
      jsr Trick
      jsr Trick
      jsr Trick


      ldy #107
next2:
      sta WSYNC
      lda #0
      sta GRP0
      sta GRP1
      dey
      bpl next2


      STA VBLANK ; Make TIA output invisible,
      lda #30
      sta TIM64T
OverscanWait:
      lda     INTIM
      bne     OverscanWait

      JMP  MainLoop      ;Continue forever.


Trick:
      sta WSYNC
      ldy #10
next1:
      sta WSYNC
      lda Table2,y
      sta GRP0
      lda Table1,y
      sta GRP1
;      nop
;      nop
      nop
      ldx #RESP1
      txs
      JSR nextinstruction1
nextinstruction1
      txs
      JSR nextinstruction2
nextinstruction2
      txs
      JSR nextinstruction3
nextinstruction3
      txs
      JSR nextinstruction4
nextinstruction4
      txs
      JSR nextinstruction5
nextinstruction5
      txs
      JSR nextinstruction6
nextinstruction6
      dey
      bpl next1

      sta WSYNC
      lda #0
      sta GRP0
      sta GRP1
      sta WSYNC
      sta WSYNC
      sta WSYNC
      sta WSYNC
      sta WSYNC
      ldx #$fd
      txs
      rts




Table1: .byte #%11100000
        .byte #%01100000
        .byte #%01100000
        .byte #%01100000
        .byte #%11100000
        .byte #%11100000
        .byte #%11000000
        .byte #%10000000
        .byte #%11000000
        .byte #%11100000
        .byte #%01100000
Table2: .byte #%00000111
        .byte #%00000110
        .byte #%00000110
        .byte #%00000110
        .byte #%11111111
        .byte #%11111111
        .byte #%01110011
        .byte #%00100001
        .byte #%01110011
        .byte #%11111111
        .byte #%11111110

	org $FFFC
	.word Start
	.word Start

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