Re: [stella] Instruction timing tip

Subject: Re: [stella] Instruction timing tip
From: "Eric Ball" <ericball@xxxxxxxxxxxx>
Date: Fri, 8 Oct 2004 20:23:23 -0400
Ahh, but the 6502 is pipelined.  The result writeback (to a register)
happens at the same time as the next instruction byte fetch/decode.

LDA $80
ADC #10
STA $80

1 fetch LDA
2 fetch $80
3 fetch [$80]
4 update A, fetch ADC
5 fetch #$10
6 update A, fetch STA
7 fetch $80
8 store [$80]

For why does RTS take 6 cycles, the answer is it reuses some of the JSR
microcode.  Check the archives, I did a post on this a while back.

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