>Note: there may be TIA limitations which would require the VSYNC to be
>asserted (and released) earlier, i.e. immediately after STA WSYNC.
I'm looking at the TIA schematics now. There are no such limitations
because VSYNC appears to be basically asynchronous on the TIA, that is, its
output is not latched with any sort of clock. It is latched, but the latch
is made of a couple of FETs and inverters and tied to no synchronous event.
In fact, it appears that VSYNC is the only register with such a latch whose
output is totally asynchronous (all other such latches are tied to the
system clock or color clock in some way.) Because of this, there a
possibility that gate delays in this latch are causing a high impedence
state for a short time, maybe 5-20 ns or so depending on the gate delay.
This state only seems possible (based on my limited knowledge of FETs and
TTL inverters) when the latched value and the newly written value are both
1. If indeed true, this high impedence state might cause a flutter in the
composite sync signal which, although short, could be long enough to confuse
the TV.
I can't say why VBLANK would affect VSYNC. except that they happen to be
physically close to one another in the schematic and this may indicate that
they are also close together in the chip, which could have the secondary
effect of making the monetary high-Z state to just go high. Other than this
wild speculation, I see nothing on the schematics to indicate any crossover
effect at all.
Also, it appears from the schematics that there is nothing that would cause
syncing problems when asserting VBLANK at weird times. In fact it appears
that we can call VBLANK any time we want, even in the middle of a scanline.
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