[stella] Clock skew...

Subject: [stella] Clock skew...
From: "C. Bond" <cbond@xxxxxxxxxxxxx>
Date: Fri, 17 Jun 2005 14:15:46 -0400
According to the docs I have, the time lag (delay) between
the CPU phase 0 clock, generated by the TIA, and the CPU
phase 2 clock, generated by the 6507, may be as much as
150nsec. This seems excessive. Has anyone ever measured the
difference? I would appreciate any input from someone with
other information or the ability to 'scope the hardware.


C. Bond

Democracy: The triumph of popularity over principle.

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