Re: [stella] Clock skew...

Subject: Re: [stella] Clock skew...
From: Chris Wilkson <ecwilkso@xxxxxxx>
Date: Fri, 17 Jun 2005 15:31:07 -0400
I can't measure right now....I haven't recovered from the latest move yet.
But my docs agree with yours and the numbers you quote seem reasonable.

The 65xx core generates non-overlapping clocks, Phi1 and Phi2.  These
are both generated from the Phi0 input, I would guess with an internal
analog delay.  So the single signal to signal delay must be doubled.
The specs I have for the 2Mhz 650xA say 75ns max delay.  So that's ~37ns
from Phi0 to Phi1 or Phi2, and ~37ns from that signal to the other one.
Not a lot considering the minimum allowable clock period is 500ns.
(and in our case it's 840ns)

I'm sure they padded the spec substantially from what they *really* thought
it would be.  Partly to account for variations in chip manufacturing, but
moreso to account for motherboard components (the pullup resistors for the
open-drain outputs) that were beyond their control.  So they padded the
number to 75ns.  (Which is a healthy 15% design margin, BTW.)  And the Atari
guys seem to have padded it a bit more.  Doubled it in fact.

("Only the paranoid survive." - Andy Grove)

The Phi0 clock is only used by the 650x.  Everything else is based off
of Phi2.  So the Phi0-Phi2 delay isn't really important to the overall

I'll try to scope the lag sometime in the next week or so.  If you don't
hear back by the end of next week, kindly remind me.  :)


On Fri, 17 Jun 2005, C. Bond wrote:

> According to the docs I have, the time lag (delay) between
> the CPU phase 0 clock, generated by the TIA, and the CPU
> phase 2 clock, generated by the 6507, may be as much as
> 150nsec. This seems excessive. Has anyone ever measured the
> difference? I would appreciate any input from someone with
> other information or the ability to 'scope the hardware.
> Thanks,
> C. Bond
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