Re: [stella] RSYNC

Subject: Re: [stella] RSYNC
From: Mark De Smet <de-smet@xxxxxxxxxxxxxxx>
Date: Sat, 3 Jun 2000 18:43:31 -0500 (CDT)
> Question:
> Here's a tough one for y'all.  Has anyone ever used RSYNC?
> I know it was used for chip testing, at least according to the manual.
> Does anyone know if this is only used to reset horizontal sync time, or if
> it could be used to alter the number of cycles needed for a specific
> scanline, too?

According to TIA spec:

"A hardware counter on this chip produces all horizontal timing (such as
sync, blank, burst) independent of the microprocessor.  This counter is
driven from an external 3.58 MHZ oscillator and has a total count of 228.
Blank is decoded as 68 counts, and sync and color burst as 16 counts."

If we assume that this is a normal counter(as opposed to a LFSR), RSYNC
would reset this counter.  The description would suggest that the counter
first goes through the blank.  I don't know if the sync and color burst
come before or after the blank, but I would guess after.  If this is true,
and if we assume that doing this has no effect on the screen, once you did
it, you would be unable to draw again for 33.333 machine cycles.  This
would probably make using this in the middle of a scan pointless.
However, you may be able to use it to blank out the right part of the
screen instead of clearing all the registers.  However, if you did, you
would be unable to use WSYNC, and would have to count the exact 76 machine
cycles, and do another RSYNC.  But then again, using VBLANK would be a
much easier way of doing this(yes you can use the VBLANK register at
anytime in the kernal to blank out the screen).  Notably, I don't know if
RSYNC actually sends stuff to the TV, if it does, then all my bets are

What I don't know, and hopefully someone who may know the video signal
better(Glenn?) could tell us, is if syncronization pulses are actually
sent to the screen everyline.  I am unfamiliar with the data format sent
out in composite sync.

> Is horizontal sync time the 76 macine cycles required to draw a line, or is
> it just the HBLANK period?  How would a tv screen react to a STA RSYNC
> command?

The above paragraph would suggest that horizontal sync is 16 cycles, or
5.33 machine cycles long.


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