Hmmm, do you know in what way it was buggy?
<<
The chip plot that was shown during the Stella at 20 sessions had some
human-error bugs. However, I think most of these bugs are labelled if the
stickers haven't fallen off and if you know what everything means. This was
the ORIGINAL plot from I guess late 1976 right as they were beginning to
reduce the design down to the first prototype chips.
The schematic that Curt is offering was generated much much later. It was
given to GCC to integrate into a proposed MARIA/TIA combo chip. So it's a
schematic of the final (working) TIA design.
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