>> $29D and $29E are TIM8T and TIM64T with interrupt enabled. The
>> 6507 processor in the VCS can't handle interrupts, so this isn't
>> really much different from the normal timer registers. However,
>> since the RIOT keeps the interrupt flag in an extra register
>> $285, I think), you might be able to do a wait for timer loop
>> with a BIT instruction, since the timer interrupt flag is at D7.
>
> Mmm... Could you explain that again? I don´t think that I understood
it.
>I always thought that $285 was a timer mirror, look what Dragon fire does:
>
> 12DB 2C8502 BIT $0285
> 12DE 10FB BPL $12DB
This is exactly what I tried to describe above. If you start
a timer with interrupts enabled ($29E instead of $296 for TIM64T),
then bit 7 of address $285 will go high when the timer wraps around
from $00 to $FF. Therefore the above loop will wait for the timer
to expire without having to change the content of any of the three
processor registers by loading from INTIM.
On a note to Chris:
are you sure that your RIOT map is correct. I have a data sheet
for it that says that reading from address $294 (RS-, A$, A2, R/W = 1,
A0 = 0) would get you the timer overflow register. I'm not quite sure
what it does, and I'm not sure if the VCS really has it, though.
Ciao, Eckhard Stolberg
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