Re: [stella] Midified VCS...

Subject: Re: [stella] Midified VCS...
From: "John Saeger" <john@xxxxxxxxxxx>
Date: Fri, 16 Nov 2001 23:13:16 -0800
----- Original Message -----
From: "Glenn Saunders" <cybpunks@xxxxxxxxxxx>

I actually don't know how hard it would really be to do the TIA.  To me,
when I looked at the schematics, part of the problem is that there is so
much detail.  Every little transistor and bit of *MML* is there in
excruciating detail.  On the bright side, much of it seems to be repetitive.
So maybe someone with a flair for macros and programmable logic might have
the best chance.  That way, it's easier to try out alternatives.  Of course
this is not to say that TTL would necessarily be impossible.  Or would it?
This is part of my question.  Are the weird side effects something that is
difficult or impossible to capture in a new implementation?  Is the Mickey
Mouse Logic and some weird internal timing part of the essence of it?  Or is
it possible to translate the design into modern components without much


> Being able to do it and doing it are two separate things.  The TIA
> schematics are out there, mind you, so there are no more excuses.  When
> you're done with the TIA you've got to duplicate the 6507 and the RIOT as
> well.  Who is going to be the first to actually pull this off??
> It's just too time-consuming a project, I think, to go through and
> every gate one by one, insuring that the timing remains exactly the same,
> etc...

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