Re: [stella] new member

Subject: Re: [stella] new member
From: "Carlos Lopez" <carlosflr@xxxxxxxxxxxxxxxx>
Date: Wed, 21 Aug 2002 20:17:54 -0500
----- Original Message -----
From: "Adam Thornton" <adam@xxxxxxx>
To: <stella@xxxxxxxxxxx>
Sent: Wednesday, August 21, 2002 2:10 PM
Subject: Re: [stella] new member

> I assume you are aware that there are FPGA 6502 designs, albeit without
> the right cycle count?  When I was kicking around doing a similar
> project to yours, I was considering using one of these and adapting the
> design to simply add enough delay that the clock counts were doubled in
> all cases--since your 6502 only has to run at 1MHz, this still gives you
> plenty of effective speed.

Yes, I have knowledge that there are several 6502 compatible cores
available, but as far as I know, only two of them are free (Free-6502 and
M65). Licensing a commercial 6502 core could cost several thousand dollars.
About the Free-6502, it doesn't have the right cycle count, and another
problem is that currently it doesn't support BCD arithmetic.
Maybe the M65 could be an option, but I haven't checked it. Anyway, it's
really not difficult to design a 6502-compatible core, only time consuming.

Carlos Lopez

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