Re: [stella] FE Bankswitching

Subject: Re: [stella] FE Bankswitching
From: "Eric Ball" <ericball@xxxxxxxxxxxx>
Date: Fri, 28 Feb 2003 22:03:26 -0500
Let me see if I can make it clearer (for myself at least) with a small

1234 JSR 5678

5690 RTS

# PC   S  ABus DBus
0 1234 FF 1000 JSR
1 1235 FF 1001 78
2 1236 FF 01FF (01FF)
3 1236 FF 01FF 12
4 1236 FE 01FE 36
5 1236 FD 1236 56
6 5678 FD 1678 (1678)

0 5690 FD 1690 RTS
1 5691 FD 1691 (1691)
2 5692 FD 01FD (01FD)
3 5692 FE 01FE 36
4 5692 FF 01FF 12
5 1236 FF 1236 56
6 1237 FF 1237 (1237)

I remember seeing something at one point which said that on the 6502 an RTS
is almost a twin of a JSR.  Looking at the table it's not difficult to see.
About the only significant difference is JSR updates the PC on cycle 5,
while RTS does it on cycle 4.  But back to bankswitching....

There are a couple of ways that FE bankswitching could work.  The simplest
would be for AddBus=01FF followed by 01FE selects one bank, while 01FE
followed by 01FF selects the other.  But if the existing code allows the
primary bank to JSR to subroutines in the same bank as well as switching
banks, then maybe it is watching the data bus as well.  The read immediately
following 01FE gives the bank on the JSR, and the same is also true for the

The timing of the bankswitch should also be considered.  On the JSR, the
bankswitch occurs between cycle #5 & 6.  On the RTS it can happen either
between cycles #4 & 5 or #5 & 6.  This suggests that the bankswitch hardware
has at least the "intelligence" to count cycles, since the JSR bankswitch
happens a cycle after the 01FF/01FE trigger.  (It wouldn't be too hard to
create a PLL based on the address bus LSB.)  This would also make it
possible to read the bank from the data bus.

If this were true, it should be possible to implement 32K ROMs using "FE+"
bankswitching.  Don't know how difficult the logic would be though.  It
would require more than a standard 22V10 PAL though... unless it monitors
less than the full address & data bus, hmm...  maybe only D7 D6 D5 (bank)
A12 (ROM/RAM) A8 (zero page & RIOT / stack) and A0 ( PLL ).  Load the bank
register from [D7 D6 D5] on the cycle after two consecutive A12 = 0 & A8 = 1
accesses.  Sounds possible at least.

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