Subject: Re: [stella] FE Bankswitching From: "Kroko" <Nil.Krokodil@xxxxxxx> Date: Sat, 1 Mar 2003 04:16:55 +0100 |
I found the following description of RTS on
the net
according to the document, it is the RTS of a 6510 CPU. But it is different from the decription, that was posted here on the list. It would be interesting to find out, what the real cycle order is, because this is most important ....
can anybody confirm that this is
wrong ?
RTS: +---------------+------------------+-----------------------+----------+ | Cycle | Address Bus | Data Bus |Read/Write| +---------------+------------------+-----------------------+----------+ | 1 | PBR,PC | Op Code | R | | 2 | PBR,PC+1 | Internal Operation | R | | 3 | PBR,PC+1 | Internal Operation | R | | 4 | 0,S+1 | New PCL-1 | R | | 5 | 0,S+2 | New PCH | R | | 6 | 0,S+2 | Internal Operation | R | | 1 | PBR,NewPC | New Op Code | R | +---------------+------------------+-----------------------+----------+ --Kroko
|
Current Thread |
---|
|
<- Previous | Index | Next -> |
---|---|---|
Re: [stella] FE Bankswitching, Eric Ball | Thread | [stella] i need cuttle cart softwar, Chris Wilkson |
[stella] Problems with Skeleton on , Eric Ball | Date | |
Month |