> Try this:
>
> Think of the SRAM as 128 blocks each of 1024 bytes.
> Let 3F control the first 2K of the cart's addressable space:
>
> Writing a value N with the MSB cleared (i.e. from 0 to 127) there maps
> blocks N and N+1 into the first 2K, read only (i.e. as if it were ROM).
>
> Writing a value N with the MSB set (i.e. from 128 to 255) there maps
> block N as RAM, with the first 1K as read and the second 1K as write.
>
> Let 3E control the second 2K in a similar manner:
>
> Writing a value N with the MSB cleared (i.e. from 0 to 127) there maps
> blocks N and N+1 into the second 2K, read only (i.e. as if it were ROM).
>
> Writing a value N with the MSB set (i.e. from 128 to 255) there maps
> block N as RAM, with the third 1K as read and the fourth 1K as write.
>
> Did that make sense? Now any part of the 128K SRAM can be mapped as
> RAM or ROM.
Hey that does also sound intersting. There is 512K flash-ROM AND 128K of
SRAM. I would like to be compatible with Andrews 3F stuff because the babies
are so funny :-))
What I would like to do is simply enhance and existing BS scheme such that
it is
possible to map in the 128K of RAM in addition to the 512K ROM.
I like the idea to enhance 3F because its so easy to select banks. Just
write a
number to a memory location. And then it is usable like superchip, FA or CV
.... a read port and a write port..
-Kroko
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