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Refering to the TIA schematic, page 1, section D5
There are two boxes labelled F1, which appear to be S/R latches with
inverted inputs (details for F1 are on page 1, section C1). The two
latches are used to derive Hphi1 and Hphi2.
As near as I can tell, and by looking at simulations, they are configured
in an unstable manner.
While the clock is high (OSC=1), if the one on the left is outputting
Q=1, it will set the one on the right to output Q=1, which will reset
the one on the left to Q=0, which will reset the one on the right to Q=0,
which will set the one on the left to Q=1, and so on, in an unending loop.
How is this resolved?
Of course this loop stops when OSC=0, but I find it hard to believe
that the main clocks used to drive all the LFSRs (Hphi1 and Hphi2) are
dependant on the propogation delays of the various gates. I don't think
the TIA designers would have left something that important to chance.
What am I missing?
- --
adam@xxxxxxxxxxxxxxxx http://cuddlepuddle.org/~adam
KG6GZR http://cuddlepuddle.org/~adam/resume.html
"Feminist? Why would I want to alienate half the population? I'm an egalitarian."
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