Re: [stella] TIA schematic question

Subject: Re: [stella] TIA schematic question
From: Chris Wilkson <ecwilkso@xxxxxxx>
Date: Mon, 15 Nov 2004 13:35:27 -0500 (EST)
Those are master-slave flipflops.  If you look at the F1 cell, there are
2 s-r latches there.  At no time are both those latches open.  The first
one (driven by the nor gates) is open only when clock is low.  The second
one is open only when clock is high.

Say the clock is high and there is a certain input (call it "foo") to the
F1 cell.  The first latch, L1, is closed (remembering) and its output
propagates through the second latch, L2, which is open.  When the clock
goes low, the L2 is closed (remembering) and L1 opens.  The input foo
propagates through L1 but is stopped at the input to the L2.  If foo
changes while the clock is low, it will flow through L1.  As soon as
the clock goes high again, L1 is closed and L2 is opened.  The output
of L1 flows through L2.  But because L1 is closed, even if foo changes,
it can't get through L1 until the clock goes low again.

What does this mean?  An input takes an entire clock cycle to propagate
through.  And Q and /Q can only change on the rising edge of the clock.
Their new value is determined by the values of /S and /R at the previous
falling edge of the clock.

FYI, this is how D-flipflops work too.  They are made from a cascade of
2 D-latches, with the first D-latch having /CLK as it gate input and the
second D-latch having CLK as it's gate input.


On Mon, 15 Nov 2004, Adam Wozniak wrote:

> Hash: SHA1
> Refering to the TIA schematic, page 1, section D5
> There are two boxes labelled F1, which appear to be S/R latches with
> inverted inputs (details for F1 are on page 1, section C1).  The two
> latches are used to derive Hphi1 and Hphi2.
> As near as I can tell, and by looking at simulations, they are configured
> in an unstable manner.
> While the clock is high (OSC=1), if the one on the left is outputting
> Q=1, it will set the one on the right to output Q=1, which will reset
> the one on the left to Q=0, which will reset the one on the right to Q=0,
> which will set the one on the left to Q=1, and so on, in an unending loop.
> How is this resolved?
> Of course this loop stops when OSC=0, but I find it hard to believe
> that the main clocks used to drive all the LFSRs (Hphi1 and Hphi2) are
> dependant on the propogation delays of the various gates.  I don't think
> the TIA designers would have left something that important to chance.
> What am I missing?
> - --
> adam@xxxxxxxxxxxxxxxx
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